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| STS3C2F100 N-CHANNEL 100V - 0.110 - 3A SO-8 P-CHANNEL 100V - 0.320 - 1.5A SO-8 COMPLEMENTARY PAIR STripFETTM POWER MOSFET TYPE STS3C2F100(N-Channel) STS3C2F100(P-Channel) VDSS 100 V 100 V RDS(on) < 0.145 < 0.380 ID 3.0 A 1.5 A TYPICAL RDS(on) (N-Channel) = 0.110 TYPICAL RDS(on) (P-Channel) = 0.320 STANDARD OUTLINE FOR EASY AUTOMATED SURFACE MOUNT ASSEMBLY ULTRA LOW GATE CHARGE ULTRA LOW ON-RESISTANCE SO-8 DESCRIPTION This MOSFET is the second generation of STMicroelectronis unique "Single Feature SizeTM" strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS DC MOTOR DRIVES AUDIO AMPLIFIER Ordering Information SALES TYPE STS3C2F100 MARKING S3C2F100 PACKAGE SO-8 PACKAGING TAPE & REEL ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM(*) Ptot Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Storage Temperature Max. Operating Junction Temperature N-CHANNEL 100 100 20 3.0 1.9 12 2 -55 to 150 150 1.5 1.0 6 P-CHANNEL Unit V V V A A A W C C (*) Pulse width limited by safe operating area. June 2004 . Note: P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed Rev.1.0.1 1/11 STS3C2F100 TAB.1 THERMAL DATA Rthj-amb(1) Thermal Resistance Junction-ambient 62.5 C/W (1) when mounted on 1 in2 pad of 2 oz. copper, t 10sec. ELECTRICAL CHARACTERISTICS (Tj = 25 C unless otherwise specified) TAB.2 OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 n-ch p-ch Min. 100 1 10 100 Typ. Max. Unit V A A nA VDS = Max Rating n-ch VDS = Max Rating TC = 125C p-ch VGS = 20 V n-ch p-ch TAB.3 ON Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V VGS = 10 V ID = 250 A ID = 1.5 A ID = 1.0 A n-ch p-ch n-ch p-ch Min. 2 2 0.110 0.320 0.145 0.380 Typ. Max. Unit V V TAB.4 DYNAMIC Symbol gfs (*) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 20 V VDS = 30 V ID= 1.5 A ID= 1.0 A n-ch p-ch n-ch p-ch VDS = 25V, f = 1 MHz, VGS = 0 n-ch p-ch n-ch p-ch Min. Typ. 3 4 460 705 70 83 30 30 Max. Unit S S pF pF pF pF pF pF 2/11 STS3C2F100 ELECTRICAL CHARACTERISTICS (continued) TAB.5 SWITCHING ON Symbol td(on) tr Parameter Turn-on Delay Time Test Conditions N-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 P-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 (Resistive Load, Figure 1) N-CHANNEL VDD=80V ID=3A VGS=10V n-ch p-ch n-ch p-ch Min. Typ. 16 14 25 20 Max. Unit ns ns ns ns Rise Time Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge n-ch p-ch 15 20 3.7 2.0 4.7 6.0 20 27 nC nC nC nC nC nC n-ch P-CHANNEL VDD = 80V ID = 1.5A VGS= 10V p-ch n-ch (see test circuit, Figure 2) p-ch TAB.6 SWITCHING OFF Symbol td(off) tf Parameter Turn-off Delay Time Test Conditions N-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 P-CHANNEL VDD = 50 V ID = 1.5 A VGS = 10 V RG = 4.7 (Resistive Load, Figure 1) n-ch p-ch n-ch p-ch Min. Typ. 32 33 20 7.5 Max. Unit ns ns ns ns Fall Time TAB.7 SOURCE DRAIN DIODE Symbol ISD ISDM (*) VSD() Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage ISD = 3 A ISD = 1.5 A VGS = 0 VGS = 0 Test Conditions n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch p-ch 90 65 230 175 5.0 5.4 Min. Typ. Max. 3.0 1.5 12 6.0 1.2 1.2 Unit A A A A V V ns ns nC nC A A trr Qrr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current N-CHANNEL ISD = 3 A di/dt = 100A/s VDD = 50 V Tj =150 oC P-CHANNEL ISD = 1.5 A di/dt = 100A/s VDD = 50 V Tj =150 oC (see test circuit, Figure 3) () Pulsed: Pulse duration = 300 s, duty cycle 1.5 %. (*) Pulse width limited by safe operating area. 3/11 STS3C2F100 Safe Operating Area n-ch Thermal Impedance n-ch Output Characteristics n-ch Transfer Characteristics n-ch Transconductance n-ch Static Drain-source On Resistance n-ch 4/11 STS3C2F100 Gate Charge vs Gate-source Voltage n-ch Capacitance Variations n-ch Normalized Gate Threshold Voltage vs Temperature n-ch Normalized on Resistance vs Temperature n-ch Source-drain Diode Forward Characteristics n-ch Normalized Breakdown Voltage vs Temperature n-ch 5/11 STS3C2F100 Safe Operating Area p-ch Thermal Impedance p-ch Output Characteristics p-ch Transfer Characteristics p-ch Transconductance p-ch Static Drain-source On Resistance p-ch 6/11 STS3C2F100 Gate Charge vs Gate-source Voltage p-ch Capacitance Variations p-ch Normalized Gate Threshold Voltage vs Temperature p-ch Normalized on Resistance vs Temperature p-ch Source-drain Diode Forward Characteristics p-ch Normalized Breakdown Voltage vs Temperature p-ch 7/11 STS3C2F100 Fig. 1: Switching Times Test Circuits For Resistive Load Fig. 2: Gate Charge test Circuit Fig. 3: Test Circuit For Diode Recovery Behaviour 8/11 STS3C2F100 SO-8 MECHANICAL DATA DIM. MIN. A a1 a2 a3 b b1 C c1 D E e e3 F L M S 3.8 0.4 4.8 5.8 1.27 3.81 4.0 1.27 0.6 8 (max.) 0.14 0.015 5.0 6.2 0.65 0.35 0.19 0.25 0.1 mm TYP. MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 0.188 0.228 0.050 0.150 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 0016023 9/11 STS3C2F100 Revision History Date Friday 18 June 2004 Revision 1.0.1 FIRST ISSUE Description of Changes 10/11 STS3C2F100 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 11/11 |
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